Chip and calibration method thereof

ABSTRACT

A calibration method includes generating, by a digital-to-analog converter of a chip, a first predetermined voltage and a second predetermined voltage and outputting the same to an analog-to-digital-converter of the chip to generate a first digital code difference; determining a variation parameter according to the first digital code difference and one of a plurality of second digital code differences stored in a look up table of a memory unit of the chip; driving, by an external testing system, the digital-to-analog converter to generate the first predetermined voltage and the second predetermined voltage and output the same to the analog-to-digital-converter to generate a target code difference; and multiplying the second digital code differences with the variation parameter to calibrate a gain of the analog-to-digital converter according to the target code difference.

This application claims priority to Taiwan Application Serial Number,104131616, filed Sep. 24, 2015, which is herein incorporated byreference.

BACKGROUND

Technical Field

The present disclosure relates to a chip. More particularly, the presentdisclosure relates to a chip having an analog-to-digital converter and acalibration method thereof.

Description of Related Art

Chips having analog-to-digital converters (ADC) are commonly utilized invarious image applications to convert data signals, from an externalvideo source, to digital data for digital processing implemented bysubsequent image processing circuits.

Different application environments of the chip or process variationsintroduced during manufacture bring a negative impact on the voltagerange which could be resolved by an ADC or on the resolution of the ADC.For example, the resolved image may have a color cast, an insufficientbrightness, etc.

In some approaches, before the chips are utilized, testing signals aredirectly input to the chips for performing a recursive test tocontinuously calibrate the analog-to-digital converter until the ADCmeets the required specification. However, such an approach requires alarge amount of testing time and human resources, as well as a specifictesting signal source, which results in a low efficiency.

SUMMARY

An aspect of the present disclosure is to provide a chip. The chipincludes an analog-to-digital converter, a memory unit and adigital-to-analog converter. The memory unit is configured to store alook up table. The look up table stores first digital code differencesand is calibrated according to a variation parameter. The first digitalcode differences are generated, according to a first predeterminedvoltage and a second predetermined voltage, by the analog-to-digitalconverter at a plurality of gains respectively. The digital-to-analogconverter generates the first predetermined voltage and the secondpredetermined voltage and output the same to the analog-to-digitalconverter to measure a second digital code difference generated by theanalog-to-digital converter at a first gain of the gains. The variationparameter is a ratio of the second digital code difference and one ofthe first digital code differences.

Another aspect of the present disclosure is to provide a calibrationmethod. The calibration method includes generating, by adigital-to-analog converter of a chip, a first predetermined voltage anda second predetermined voltage and outputting the same to ananalog-to-digital-converter of the chip to generate a first digital codedifference; determining a variation parameter according to the firstdigital code difference and one of a plurality of second digital codedifferences stored in a look up table of a memory unit of the chip;driving, by an external testing system, the digital-to-analog converterto generate the first predetermined voltage and the second predeterminedvoltage and output the same to the analog-to-digital-converter togenerate a target code difference; and multiplying the second digitalcode differences with the variation parameter, to calibrate a gain ofthe analog-to-digital converter according to the target code difference.

Yet another aspect of the present disclosure is to provide a chip. Thechip includes an analog-to-digital converter, a memory unit, adigital-to-analog converter, and a firmware. The memory unit stores afirst digital code difference. The first digital code difference is adigital code difference generated by the analog-to-digital converteraccording to a first voltage and a second voltage at a gain. Thedigital-to-analog converter generates the first voltage and the secondvoltage and output the same to the analog-to-digital converter tomeasure a second code difference generated by the analog-to-digitalconverter at the gain. The ratio of the second digital code differenceand the first digital code difference is a variation parameter. Thefirmware calibrates the gain of the analog-to-digital converteraccording to the variation parameter, and an initial reference voltageand a maximum reference voltage of the analog-to-digital converter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a chip according to some embodiments ofthe present disclosure;

FIG. 2 is a flow chart of a calibration method according to someembodiments of the present disclosure;

FIG. 3A is a schematic diagram illustrating operations of building alook up table in FIG. 1 according to some embodiments of the presentdisclosure; and

FIG. 3B is a schematic diagram illustrating operations of adjusting aquantization range of an analog-to-digital converter in FIG. 1 accordingto some embodiments of the present disclosure.

DETAILED DESCRIPTION

FIG. 1 is a schematic diagram of a chip 100 according to someembodiments of the present disclosure. The chip 100 includes ananalog-to-digital conversion module 120, a memory unit 140, and adigital-to-analog conversion module 160.

The analog-to-digital conversion module 120 includes analog-to-digitalconverters (ADCs) 122, 124, and 126. Each of the ADCs 122, 124, and 126generates a corresponding digital code DC according to a correspondingdata signal VIN, which lets the subsequent circuits perform digital dataprocessing on the digital code DC. For example, when the chip 100 isapplied in image processing, the external signal source is an RGB signalsource. The ADCs 122, 124, and 126 are able to process a data signalVIN_R corresponding to red, a data signal VIN_G corresponding to green,and a data signal VIN_B corresponding to blue, to generate the digitalcodes DC_R, DC_G, and DC_B respectively. In other words, in someembodiments, the analog-to-digital conversion module 120 utilizesmulti-channel ADCs to process data signals of different colorsrespectively. Accordingly, subsequent circuits are able to performoperations of image processing based on the digital code DC_R, thedigital code DC_G and the digital code DC_B.

In some embodiments, the external signal source may be various types ofvideo signal sources, e.g., Yprpb, or other types of signal sources.

In various embodiments, each of the ADCs 122, 124, and 126 may be an ADChaving different types of architectures, such as a flash ADC or asuccessive approximation ADC.

The memory unit 140 stores look up tables 142 and firmware 144 forcontrolling the chip 100. In some embodiments, each look up table 142 isconfigured to store digital code differences DF1 (as shown in table 1below), in which the digital code differences DF1 are the codedifferences between digital codes (e.g., H0-H8 i and L0-L8 in table 1).The digital codes H0-H8 and L0-L8 are generated, according to apredetermined voltage VD1 and a predetermined voltage VD2, by the ADCs122, 124, and 126 at a plurality of different gains respectively. Thefirmware 144 configures the related parameters of the analog-to-digitalconversion module 120 and digital-to-analog conversion module 160, e.g.,a gain of the ADC 122, an input signal of the DAC 162, etc. For example,the firmware 144 outputs control codes C1 and C2 to control thedigital-to-analog conversion module 160 to output the predeterminedvoltages VD1 and VD2.

In some embodiments, the memory unit 140 may be a register. In someother embodiments, the look up table is configured to be written onceinto the memory unit 140. In some embodiments, the memory unit 140 mightbe a one-time programmable memory.

The digital-to-analog conversion module 160 includes digital-to-analogconverters (DACs) 162, 164, and 166. The DACs 162, 164, and 166 generatethe predetermined voltages VD1 and VD2 and output the same to each ofthe ADCs 122, 124, and 126 according to the control codes C1 and C2.Accordingly, the ADCs 122, 124, and 125 are able to generate digitalcode differences DF2 (not shown) according to the predetermined voltagesVD1 and VD2. In some embodiments, the digital code differences DF1 andDF2 are configured to be measured under different environments. As aresult, with the digital code differences DF1 and DF2, a variationparameter CR corresponding to an actual operating environment of thechip 100 can be determined. In some embodiments, the variation parameteris configured to be a ratio of the digital code differences DF2 to thedigital code differences DF1, which is expressed as CR=DF2/DF1.

In some embodiments, each of the DACs 162, 164, and 166 may be a DAChaving various different types of architectures, such as a resistorstring DAC or a current-steering DAC.

In some embodiments, the look up tables 142 can be calibrated accordingto the variation parameter CR to eliminate various offsets, e.g.,voltage offsets or power variations, introduced from the actualoperating environment of the chip 100. As a result, the operationalreliability and the accuracy of the chip 100 are able to be improved.

In some embodiments, the number of the ADCs in the analog-to-digitalconversion module 120 and the number of the DACs in thedigital-to-analog conversion module 160 can be adjusted according theactual applications of the chip 100.

Reference is now made to both of FIG. 1 and FIG. 2 to illustrate theoperations of the chip 100 and a calibration method 200. For simplicity,the following description is given based on the operations of the ADC122 and the DAC 162.

In operation S210, the DAC 162 generates the predetermined voltages VD1and VD2 and outputs the same to the ADC 122 to measure the digital codedifferences DF1, in which the code differences DF1 are generated,according to the predetermined voltages VD1 and VD2, by the ADC 122 atdifferent gains.

In operation S220, the look up table 142 is set up in the memory unit140, in which the look up table 142 includes the digital codedifferences DF1.

For example, a user A1 is a manufacturer or a developer of the chip 100.In some embodiments, as shown in FIG. 3A, the DAC 162 is driven by adriving voltage, e.g., about 3.3 Volts, provided from a testing tool ofthe user A1, in order to generate the predetermined voltage VD1 (e.g.,about 0.85 Volts) and the predetermined voltage VD2 (e.g., about 0.55Volts), and output the same to the ADC 122. The testing tool of the userA1 is able to adjust the ADC 122 by the firmware 144 of the chip 100,such that the digital codes H0-H8 and L0-L8 generated, according to thepredetermined voltages VD1 and VD2, by the ADC 122 at a plurality ofdifferent gains respectively can be measured. The digital codedifferences DF1 are then able to be determined from the differencebetween the digital codes H0-H8 and L0-L8. Accordingly, the user A1 canset up the look up table as shown in table 1 according the informationabove. As shown in FIG. 3A, the higher the gain of the ADC 122, thesmaller the digital code differences DF1 in the same voltage range.Effectively, in some embodiments, by adjusting the gain of the ADC 122,a step size of the ADC 122 is adjusted. For example, when the gain isset to be 1, the predetermined voltage VD1 corresponds to a digital codeH0 (0x2ff), and the predetermined voltage VD2 corresponds to a digitalcode L0 (0x000). When the gain is set to be 32, the predeterminedvoltage VD1 corresponds to a digital code H1 (0x1ff), and thepredetermined voltage VD2 corresponds to a digital code L0 (0x200). Suchvalues of the gain and the digital codes above are given forillustrative purposes only, and the present disclosure is not limitedthereto.

TABLE 1 Gain 1 32 64 128 192 0.85 Volts H0 H1 H2 H3 H4 0.55 Volts L0 L1L2 L3 L4 DF1 H0 − L0 H1 − L1 H2 − L2 H3 − L3 H4 − L4 Gain 256 352 448511 — 0.85 Volts H5 H6 H7 H8 — 0.55 Volts L5 L6 L7 L8 — DF1 H5 − L5 H6 −L6 H7 − L7 H8 − L8 —

In some embodiments, the DAC 162 is configured to employ resistors todivide a driving voltage, so as to generate the predetermined voltagesVD1 and VD2 according to the driving voltage. By measuring the digitalcode differences DF1 generated, according to the predetermined voltagesVD1 and VD2, by the ADC 122, the voltage offsets introduced fromvariations in the resistors can be reduced.

Referring back to FIG. 2, in operation S230, a user A2 is able toconnect an external testing system with the chip 100, so as to drive theDAC 162 by the external testing system to generate the predeterminedvoltages VD1 and VD2 and output the same to the ADC 122.

In operation S240, the firmware 144 determines the variation parameterCR according to the digital code differences DF2, in which the digitalcode differences DF2 are generated by the ADC 122 according to thepredetermined voltages VD1 and VD2.

For example, the user A2 may be a hardware developer of the chip 100.The user A2 may be able to dispose the chip 100 on a circuit board, andset the gain of the ADC 122 to a first gain among a plurality of gains.In some embodiments, the first gain is a middle value, e.g., 192 intable 1, of the gains, or any gain within a linear range of the gains,and is sufficient to linearly indicate the relationship between thegains of the ADC 122 and the digital code differences generated by theADC 122. The DAC 162 is driven to generate the predetermined voltagesVD1 and VD2 to the ADC 122, such that the ADC 122 on the circuit boardgenerates the digital code difference DF2 at the first gain. Thefirmware 144 then divides the digital code difference DF2 by the digitalcode difference DF1 in table 1 corresponding to the first gain todetermine the variation parameter CR.

In operation S250, the user A2 connects the chip 100 to the externaltesting system, in order to test the quantization range of the ADC 122.For example, the user A2 disposes the chips 100 on circuit boards (e.g.,printed circuit boards), and connects them to the external testingsystem, as shown in FIG. 3A, to input a testing signal VTEST to the ADC122. The amplitude range of the testing signal VTEST is about 0.4-1.1volts. In other words, the signal amplitude of the testing signal VTESTis about 0.7 volts. A voltage of 0.4 volts corresponds to the darkestimage, and a voltage of 1.1 volts corresponds to the brightest image.The user A2 can adjust the gain of the ADC 122 with the digital code DCgenerated by the ADC 122 according to the testing signal VTEST, in orderto ensure that the quantization range of the ADC 122 can be utilized toanalyze the voltage range of 0.4-1.1 volts. In some embodiments, afterthe quantization range of the ADC 122 is calibrated, the minimum digitalcode outputted by the ADC 122 corresponds to 0.4 volts, and the maximumdigital code outputted by the ADC 122 corresponds to 1.1 volts.

In some embodiments, the quantization range of the ADC 122 is adjustedby adjusting at least one internal reference voltage of the ADC 122, orby adjusting a minimum step size (alternatively referred to as leastsignificant bit, LSB) that is able to be resolved by the ADC 122.

In operation S260, after the quantization range is adjusted, the DAC 162is driven by the external testing system to generate the predeterminedvoltages VD1 and VD2 and output the same to the ADC 122, in order togenerate a target code difference.

In operation S270, the firmware 144 multiplies the digital codedifferences DF1 with the variation parameter CR to calibrate the gain ofthe ADC 122 according to the target code differences.

For illustration, similar to the operations illustrated in FIG. 3A,after the quantization range is adjusted, the gain of the ADC 122 isfirst fixed. The user A2 connects the external testing system to thecircuit boards having the chip 100 to generate digital code differencesaccording to the predetermined voltages VD1 and VD2. The user A2 canaverage such digital code differences to determine the target codedifference corresponding to the external testing system, and then updatethe target code difference to the firmware 144. In some embodiments,cell variations are present in the circuit boards, or offsets arepresent in the driving voltages generated from different testing tools.By averaging the digital code differences, the various variations areable to be essentially canceled from the target code difference.

Furthermore, the firmware 144 may be configured to perform aninterpolation to calibrate the gain of the ADC 122. The firmware 144reads the digital code differences DF1 from table 1, and then multipliesthe digital code differences DF1 with the variation parameter CR.Accordingly, the firmware 144 can further select two digital codedifferences DF1 from the adjusted digital code differences DF1 accordingto the target code differences, in order to perform the interpolationaccording to the gains to calibrate the ADC 122, in which the gainscorrespond to the two of the adjusted digital code differences DF1.

For example, as shown in table 1, when the firmware 144 determines thatthe target code difference falls between the digital code differences(H3−L3)*CR and (H4−L4)*CR, the firmware 144 then performs theinterpolation in the numerical range of gains 128-192 to determine thegain of the ADC 122.

Alternatively, the firmware 144 multiplies the digital code differencesDF1 in table 1 with the variation parameter CR to generate the look uptable, which is illustrated as table 2 below, and stores the same in thememory unit 140. Accordingly, the firmware 140 is then able to determinethe gain of the ADC 122 according to the look up table, as illustratedin the table 2, and the target code difference.

TABLE 2 Gain 1 32 64 128 192 DF2 (H0 − L0) × (H1 − L1) × (H2 − L2) × (H3− L3) × (H4 − CR CR CR CR L4) × CR Gain 256 352 448 511 — DF2 (H5 − L5)× (H6 − L6) × (H7 − L7) × (H8 − L8) × — CR CR CR CR

With such an arrangement, the chip 100 is able to self-calibrate the ADC122 according to the predetermined voltages VD1 and VD2 generated by theinternal DAC 162 without performing the operations 8210 and S220 again.Accordingly, savings are realized with respect to the time and cost fortesting the chip 100.

In some other embodiments, the firmware 144 is configured to store aninitial reference voltage VREF0 and a maximum reference voltage VREFT,and calibrate the gain of the ADC 122 according the variation parameterCR, the initial reference voltage VREF0, and the maximum referencevoltage VREFT.

For example, compared with the embodiments of storing the digital codedifferences DF1 and DF2, in this embodiment, the firmware 144 stores thecalibration flow corresponding to the equations (1) and (2) below:

$\begin{matrix}{{TARGET} = {\frac{\left( {{{VD}\; 1} - {{VD}\; 2}} \right)}{{VREF} \times {AF}} \times {BITS}}} & (1)\end{matrix}$

$\begin{matrix}{{VREF} = {{{VREF}\; 0} + \frac{{GAIN} \times {VREFT}}{GAINT}}} & (2)\end{matrix}$

-   -   where TARGET is the target code difference, VD1 and VD2 are the        predetermined voltages, VREF is an internal reference voltage of        the ADC 122, AF is an attenuation factor for the ADC 122        transmitting signals, BITS is an effective number of bits of the        ADC 122, VREF0 is the initial reference voltage of the reference        voltage VREF, VREFT is the maximum reference voltage of the        reference voltage VREF, GAIN is the gain of the ADC 122, and        GAINT is a maximum gain of the ADC 122. In various embodiments,        the value of the effective number of bits BITS and the value of        the attenuation factor AF are able to be measured in advance,        and then set up in the firmware 144.

In this embodiment, the user A1 can set the gain of the ADC 122 as zeroand the maximum gain GAINT, in order to determine the initial referencevoltage VREF0 and the maximum reference voltage VREFT. The user A1 thenupdates the aforementioned parameters, which includes, for example, themaximum gain GAINT, the initial reference voltage VREF0, and the maximumreference voltage VREFT, to the firmware 144. After the variationparameter CR is determined (i.e., after the operation S240 isperformed), the user A2 can input a first target code difference to thefirmware 144. The firmware 144 divides the first target code differenceby the variation parameter CR to obtain a second target code difference.The firmware 144 then substitutes the second target code difference intothe equation (1) to obtain the corresponding reference voltage VREF.Furthermore, the firmware 144 substitutes the corresponding referencevoltage VREF into the equation (2) to determine the calibrated gainGAIN.

In some embodiments, the external testing system includes a modegenerator, a logic analyzer, and/or other suitable measurementequipment.

The embodiments illustrated with an image application above are only forillustrative purposes only. Various applications that are able to beapplied with the chip 100 can also be calibrated by using thecalibration method 200.

As described above, the chip and the calibration method provided in thepresent disclosure can be self-calibrated via the internal DAC, suchthat the time for testing the chip and human resource costs associatedtherewith can be reduced.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentdisclosure without departing from the scope or spirit of the disclosure.In view of the foregoing, it is intended that the present disclosurecover modifications and variations of this disclosure provided they fallwithin the scope of the following claims.

What is claimed is:
 1. A chip, comprising: an analog-to-digitalconverter; a memory unit configured to store a look up table, whereinthe look up table is configured to store a plurality of first digitalcode differences, and is configured to be calibrated according to avariation parameter, wherein the first digital code differences aregenerated, according to a first predetermined voltage and a secondpredetermined voltage, by the analog-to-digital converter at a pluralityof gains respectively; and a digital-to-analog converter configured togenerate the first predetermined voltage and the second predeterminedvoltage and output the same to the analog-to-digital converter tomeasure a second digital code difference generated by theanalog-to-digital converter at a first gain among the plurality of thegains; wherein the variation parameter is a ratio of the second digitalcode difference and one of the first digital code differences.
 2. Thechip of claim 1, wherein the analog-to-digital converter is furtherconfigured to have the first gain, and the digital-to-analog converteris configured to be driven by an external testing system to generate thefirst predetermined voltage and the second predetermined voltage andoutput the same to the analog-to-digital converter for measuring thesecond digital code difference of the analog-to-digital converter, andthe one of the first digital code differences corresponds to the firstgain.
 3. The chip of claim 1, wherein the analog-to-digital converter isfurther configured to receive a testing signal from an external testingsystem to adjust a quantization range of the analog-to-digitalconverter; wherein after the quantization range is adjusted, thedigital-to-analog converter is further driven by the external testingsystem to generate the first predetermined voltage and the secondpredetermined voltage and output the same to the analog-to-digitalconverter, and the analog-to-digital converter is further configured togenerate a target code difference corresponding to the external testingsystem according to the first predetermined voltage and the secondpredetermined voltage.
 4. The chip of claim 3, wherein the memory unitis further configured to store a firmware, and the firmware isconfigured to multiply the first digital code differences in the look uptable with the variation parameter, and to select, according to thetarget code difference, two of the multiplied first digital codedifferences for performing an interpolation to calibrate theanalog-to-digital converter.
 5. The chip of claim 3, wherein the memoryunit is further configured to store a firmware, and the firmware isconfigured to store an initial reference voltage and a maximum referencevoltage corresponding to the analog-to-digital converter, and tocalibrate the gain of the analog-to-digital converter according to thevariation parameter, the initial reference voltage and the maximumreference voltage.
 6. The chip of claim 5, wherein the gain of theanalog-to-digital converter is set as zero to obtain the initialreference voltage, the gain of the analog-to-digital converter is set asa maximum gain to obtain the maximum reference voltage, and the initialreference voltage and the maximum reference voltage are further updatedto the memory unit.
 7. The chip of claim 3, wherein the memory unit isfurther configured to store a firmware, the firmware is furtherconfigured to obtain a corresponding reference voltage according to thevariation parameter and the target code difference, and calibrate thegain of the analog-to-digital converter according to the correspondingreference voltage.
 8. A calibration method, comprising: generating, by adigital-to-analog converter of a chip, a first predetermined voltage anda second predetermined voltage and outputting the same to ananalog-to-digital-converter of the chip to generate a first digital codedifference; determining a variation parameter according to the firstdigital code difference and one of a plurality of second digital codedifferences stored in a look up table of a memory unit of the chip;driving, by an external testing system, the digital-to-analog converterto generate the first predetermined voltage and the second predeterminedvoltage and output the same to the analog-to-digital-converter togenerate a target code difference; and multiplying the second digitalcode differences with the variation parameter to calibrate a gain of theanalog-to-digital converter according to the target code difference. 9.The calibration method of claim 8, further comprising: inputting thefirst predetermined voltage and the second predetermined voltage to theanalog-to-digital converter for measuring the second digital codedifferences to set up the look up table; wherein the second digital codedifferences are differences between a first digital code and a secondcode, and the first digital code and the second code are generated bythe analog-to-digital converter according to the first predeterminedvoltage and the second predetermined voltage, respectively, at differentgains.
 10. The calibration method of claim 9, wherein the one of thesecond digital code differences corresponds to a first gain of thegains, the first gain is approximately an average value of the gains,and the operation of generating the first digital code differencefurther comprises: setting the gain of the analog-to-digital converterto the first gain.
 11. The calibration method of claim 8, wherein theoperation of determining the variation parameter comprises: dividing thefirst digital code difference by the one of the second digital codedifferences to obtain the variation parameter.
 12. The calibrationmethod of claim 8, wherein the operation of calibrating the gain of theanalog-to-digital converter comprises: selecting two of the multipliedsecond code digital differences according to the target code differencefor performing an interpolation to calibrate the analog-to-digitalconverter.
 13. The calibration method of claim 8, wherein the operationof calibrating the gain of the analog-to-digital converter comprises:calibrating the gain of the analog-to-digital converter according to thevariation parameter, an initial reference voltage and a maximumreference voltage, wherein the initial reference voltage and the maximumreference voltages correspond to the analog-to-digital converter. 14.The calibration method of claim 13, wherein the operation of calibratingthe gain of the analog-to-digital converter comprises: setting the gainof the analog-to-digital converter as zero to obtain the initialreference voltage; setting the gain of the analog-to-digital converterthe gain of the analog-to-digital converter as a maximum gain to obtainthe maximum reference voltage; and updating the initial referencevoltage and the maximum reference voltage to the memory unit.
 15. Thecalibration method of claim 14, further comprising: obtaining acorresponding reference voltage according to the variation parameter andthe target code difference; and calibrating the gain of theanalog-to-digital converter according to the corresponding referencevoltage.
 16. A chip, comprising: an analog-to-digital converter; amemory unit configured to store a first digital code difference, whereinthe first digital code difference is a digital code difference generatedby the analog-to-digital converter according to a first voltage and asecond voltage at a gain; a digital-to-analog converter configured togenerate the first voltage and the second voltage, and to output thesame to the analog-to-digital converter to measure a second codedifference generated by the analog-to-digital converter at the gain,wherein the ratio of the second digital code difference and the firstdigital code difference is a variation parameter; and a firmwareconfigured to calibrate the gain of the analog-to-digital converteraccording to the variation parameter and an initial reference voltageand a maximum reference voltage of the analog-to-digital converter. 17.The chip of claim 16, wherein the gain of the analog-to-digitalconverter is set as zero to obtain the initial reference voltage, thegain of the analog-to-digital converter is set as a maximum gain toobtain the maximum reference voltage, and the initial reference voltageand the maximum reference voltage are further updated, by the externaltesting system, to the memory unit.
 18. The chip of claim 16, whereinthe gain of the analog-to-digital converter, the initial referencevoltage, and the maximum reference voltage are satisfied with thefollowing equation:${{VREF} = {{{VREF}\; 0} + \frac{{GAIN} \times {VREFT}}{GAINT}}},$ whereVREF is an internal reference voltage of the analog-to-digitalconverter, VREF0 is the initial reference voltage, VREFT is the maximumreference voltage, GAIN is the gain of the analog-to-digital converter,and GAINT is the maximum gain.
 19. The chip of claim 16, wherein thefirmware is further configured to obtain a corresponding referencevoltage according to the variation parameter and a target codedifference, and calibrate the gain of the analog-to-digital converteraccording to the corresponding reference voltage.
 20. The chip of claim19, wherein the corresponding reference voltage and the target codedifference are satisfied with the following equation:${{TARGET} = {\frac{{{VD}\; 1} - {{VD}\; 2}}{{VREF} \times {AF}} \times {BITS}}},$where TARGET is a ratio of the target code difference to the variationparameter, VD1 is the first voltage, VD2 is the second voltage, VREF isan internal reference voltage of the analog-to-digital converter, AF isan attenuation factor of the analog-to-digital converter, and BITS is aneffective number of bits of the analog-to-digital converter.